FPGA verilog

$10-30 USD

Imefungwa

Imechapishwa

about 5 years ago

$10-30 USD

Kulipwa wakati wa kufikishwa

Using ModelSim or Quartus II for solving some problems i am working on

Electrical Engineering

Kitambulisho cha mradi: 18870977

Kuhusu mradi

13 mapendekezo

Mradi wa mbali

Inatumika 5 yrs ago

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13 wafanyakazi huru wana zabuni kwa wastani $28 USD kwa kazi hii

@ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using verilog please check my profile also please message me so that we can discuss Best regards

$30 USD ndani ya siku 1

4.9

(500 hakiki)

8.1

@xaainulabideen

For more details inbox me so that we can discuss in detail. For more details inbox me so that we can discuss in detail. For more details inbox me so that we can discuss in detail.

$25 USD ndani ya siku 1

4.9

(87 hakiki)

6.7

@raulbehl

Hello! Please check my profile and reviews to know a bit about me and my work. It would be great if I could help you out

$30 USD ndani ya siku 1

4.9

(89 hakiki)

6.3

@thasleemkamila

I have well experienced in doing such kind of jobs..................................................................................................................................................................

$25 USD ndani ya siku 1

4.7

(72 hakiki)

6.1

@fjot

I have extensive knowledge on Verilog and FPGA design, also I have all the necessary tools for this assignment.

$25 USD ndani ya siku 1

5.0

(2 hakiki)

2.4

@aniljakkani3

Expert in MATLAB, Simulink,Verilog/VHDL and JOURNAL writing. I have the 8 years of experience as a MATLAB, Simulink Programmer. Working as a Reserach coordinator.

$25 USD ndani ya siku 2

4.0

(1 hakiki)

1.6

@mmdsaifudn

I am expert in modelsim.I can provide you codes with modelsim scripts.I just went through your requirements.I can do it very good for you.

$25 USD ndani ya siku 1

4.7

(2 hakiki)

1.4

@umangangrish

I have modelsim/questa and I am available 24*7 for work and proposal discussion. i am i touch with both Verilog and System Verilog. if your queries are in design or in verification i can help with both of them. the design and the test benches are ready and will be sent to you in no time. with project files and waveforms or log files included

$20 USD ndani ya siku 1

5.0

(1 hakiki)

1.0

@asicdsm

Vision-1 for free module mux_4to1_assign ( a, // input called a b, c, d, sel, // input sel used to select between a,b,c,d out); // output based on input sel input a,b,c,d; input [1:0] sel ; output out ; // When sel[1] is 0, (sel[0]? b:a) is selected and when sel[1] is 1, (sel[0] ? d:c) is taken // When sel[0] is 0, a is sent to output, else b and when sel[0] is 0, c is sent to output, else d assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a); endmodule

$50 USD ndani ya siku 1

0.0

(0 hakiki)

0.0

@tienthanhkt09

Hi there, I am an FGPA egineer. I have experienced in the FPGA design, Very high skills in Verilog and VHDL design. I also experienced in testing and debugging on FPGA boards: ML605, ZC706, Zedboard, CML-1G FPGA board,... Please take a look in my profile. Thanks & Best regards, Thanh

$35 USD ndani ya siku 1

0.0

(0 hakiki)

0.0

@balashyamu

I have experience in RTL Design with Verilog VHDL and developing test cases with Verilog Relevant Skills and Experience Verilog, VHDL, questasim, modelsim, ISIM, Vivado

$25 USD ndani ya siku 1