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Verilog Project for school

$30-250 USD

Imekamilika
Imechapishwa over 10 years ago

$30-250 USD

Kulipwa wakati wa kufikishwa
The project report must include: 1)Project definition and characterization 2)Concept development and logical design 3)Design entry using Verilog HDL and functional simulation with enough input data and verification 4)Synthesis and implementation with the .ucf file specified 5)Time simulation with enough input data 6)Downloading and Testing Design/Synthesis/Implementation MUST be done using Xilinx ISE Tools and Spartan 3E or Spartan 6(NEXYX 3) Board. I need a freelancer that can do this project and then either walk me through the process or make a video walk through. The attached file contains the project description.
Kitambulisho cha mradi: 5145782

Kuhusu mradi

9 mapendekezo
Mradi wa mbali
Inatumika 10 yrs ago

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Picha ya Mtumiaji
Hi, I'm a Verilog HDL and VHDL expert with 15+ and 13+ years experience, respectively. I have implemented more than 125 designs for third parties/clients including MSF/DCF77 decoder, FFT, RISC processors, ASIPs for image/video processing, FSMs/FSMDs for various control and data computation tasks. I have the Pong P. Chu book at my personal library (your excerpt is from the VHDL version), and have all three of the following boards: Spartan 3, 3E and 3AN starter kits. Overall, more than 40 designs implemented and verified on these boards.
$220 USD ndani ya siku 4
5.0 (2 hakiki)
3.8
3.8
Picha ya Mtumiaji
Hi dear.I can do this job..I have already worked with you I hope we can communicate better for the next [login to view URL] you want to discus please contact me.
$170 USD ndani ya siku 3
5.0 (24 hakiki)
5.0
5.0
9 wafanyakazi huru wana zabuni kwa wastani $169 USD kwa kazi hii
Picha ya Mtumiaji
Dear sir, I am the best verilog programmer at freelancer.com, i will provide you with the project in addition to online assistance using skype
$172 USD ndani ya siku 3
4.9 (389 hakiki)
7.8
7.8
Picha ya Mtumiaji
Hi, I am a graduate in EEE.I have 15 years of experience in programming,electronic design and teaching.I can do this work for you. I have good experience in verilog/vhdl FPGA design. (My current project is a 32 bit RISC processor with pipe lining.) Thanks and Regards, Prasad.M
$111 USD ndani ya siku 7
5.0 (2 hakiki)
2.5
2.5
Picha ya Mtumiaji
Hi could u tell me what do u want to implement i read the document , its not assignment its like walk trought ............................................................................................................................................................................................. and i can make a video , once i know what u want exactly
$210 USD ndani ya siku 7
0.0 (0 hakiki)
0.0
0.0
Picha ya Mtumiaji
Предложение еще не подано
$200 USD ndani ya siku 5
0.0 (0 hakiki)
0.0
0.0
Picha ya Mtumiaji
I have good skills and practical knowledge to develop the requirement for the project.I have can design with easier technique which every one can understand
$77 USD ndani ya siku 3
0.0 (0 hakiki)
0.0
0.0
Picha ya Mtumiaji
A proposal has not yet been provided
$172 USD ndani ya siku 3
0.0 (0 hakiki)
0.0
0.0

Kuhusu mteja

Bedera ya UNITED STATES
Loves park, United States
5.0
3
Njia ya malipo imethibitishwa
Mwanachama tangu Nov 5, 2013

Uthibitishaji wa Mteja

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