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    2,000 spi fpga vhdl verilog kazi zimepatikana, bei imeletwa USD

    ...use the buffered data. It sends this data with PORT write. (Because digitalWrite is slow). Timer interrupts is 50 kHz. Between timer interrupts it takes new data from SD card. We have used Arduino because it was working very good in the protoptypes. It has a simple coding and good libraries like SdFat library we use. Time to time we are getting problems. It stops reading. It can be some bug on SPI transfer or program, because it happened 5-10 times a year. Problems occurs mainly because of SD Card of customers. So we are seeking for a solution over USB to read the data. Our product works with a PC together. So we can use the PC to send data to electronics. But we cannot use Arduino Due then, because it is too slow. Possible solutions: 1. Send all the data once from PC to the ca...

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    I am a VB.Net developer creating a device that utilizes a RPi Zero W board and a 128x128 SPI OLED Display. The device has 5 Navigation buttons; Left, Right, Up, Down, Enter. i have created a VB.NET demo of a Date Entry app/script that I need in Python3. I am NOT suggesting any use of this code, this VB code when run simply demonstrates all the feature/functionality I need in the Python3 script. Please review the attached VB.NET code and provide your estimate. I have an idea of how long this will take to recreate in Python3... so, bid accordingly. High bids will be deleted immediately. if we work well together, this will lead to more work of this type.

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    I am solving ieee paper I need good verilog developer for my project

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    I have full code working on MAX10M16D. The task is to optimize the VHDL code for 10M04. I am looking for VHDL coder who has experience hdl optimization.

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    Debugging existing project of LVDS 7:1 to DDR and DDR to LVDS 7:1 using Verilog and Lattice MachX03.

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    I have completed 85% of the project. I have issue with implelenting design. Project is done using system generator 2018.a and vivad0 2019.1 . Need to fine tune desing as per specification.

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    Hello there, I need someone who can design a project on Verilog HDL using Quartus II. Hardware not needed here. Those who are available and willing to do it, please make a bid. Don't change the prices differently in the bid and in conversation. Thank you. *It is only in Verilog HDL, not in vhdl.

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    Provide mentorship & guidance on following project to complete together. 1Hr per week training over the course of Q1 of 2021. (starting in 2020 if avialable) 1. Hardware design and configuration (using external MUX and ADC,...experience a plus. 3. C / C++ (Zynq Firmware) for running the application 4. OS / RTOS (if needed) as well as privacy and security considerations. Goal will be to build fairly complex application together for embedded application. Currently working in MST timezone. Will require video to chat and discuss issues as they arise. This is a once per week discussion to further develop my knowledge of FPGA systems and to work on a cool project with a knowledgeable expert. I am easy going and am looking for a relaxed pace and good person to work with. T...

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    Wrote some vhdl code and it simulates but I want to optimize it for synthesis. Should not take longer than hour or two.

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    I need you to build it for me. Verilog and logisim skills needed.

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    I need someone with extensive knowledge in Digital Systems Design and VHDL to help me explain a few concepts

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    Assalam o alaikum, I am looking for expert in assembly language and VHDL coding. I would prefer to work with pakistani freelancers.

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    VHDL Expert needed with sound knowledge of synthesis hardware and simulations

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    verilog or vhdl implementation od PSO

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    ...shows packet arrive via tunnel, forwarded to 8.8.8.8 and send back to my device. Dump on my device shows those incoming ESP packets, but there are never decrypted. Ipsec statusall shows outgoing packets, but no incoming packets. Ping to from my Mikrotik IPsec router shows outgoing packets on my SAs, The incoming packets on my device show correct Source , Destination IP and correct SPI, but again no counting on incoming packets. Ipsec Status all: Status of IKE charon daemon (strongSwan 5.8.2, Linux 5.4.45-g334256aa8a89, armv7l): uptime: 78 minutes, since Dec 13 11:32:46 2020 malloc: sbrk 1347584, mmap 0, used 597224, free 750360 worker threads: 11 of 16 idle, 5/0/0/0 working, job queue: 0/0/0/0, scheduled: 7 loaded plugins: charon aes rc2 sha2 sha1 md5 mgf1 random nonc...

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    Devward requieres a software developer with development experience on the ESP32 working with the esp-idf to implement a driver for the KZ8794 chip which is an Ethernet switch and PHY chip. This Ethernet switch/phy is connected to the ESP32 through the RMII interface and SPI (for configuration). The Ethernet switch does not need any complex configuration for packet redirection. All packets will be redirected (all of them, doesn't matter what type of packet arrives) to the other ports expect those that come to our IP address. The tasks are the following: - Implement a driver which is able to configure the Ethernet Switch/PHY - Connect it to the ESP32 TCP/IP stack through the esp-idf APIs - Test the Ethernet Switch/PHY on our prototype Deliverables: - Source code (library) for t...

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    I need a person who know Verilog coding in electric circuits, I have attached the examples problems below

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    Разработка системы Формирования звуковых оповещений на основе FPGA,(Development of a system for generating sound notifications based on FPGA.)

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    A simple solution for displaying images on two LCDs ST7789 (without CS pin) on raspberry pi 4. They are connected to SPI0 and SPI1. The code needs to be in Python. I can only make SPI0 work, not SPI1.

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    VHDL Project Imeisha left

    I have a code to write it on ModelSim using VHDL

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    I have a project to write a code using VHDL on ModelSim

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    I have a project to write a code using VHDL on ModelSim

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    I have a project to write a code using VHDL on ModelSim

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    I have a project to write a code using VHDL on ModelSim

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    I have a project to write a code using VHDL on ModelSim

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    VHDL in ModelSim Imeisha left

    I have a project to write a code on ModelSim using VHDL

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    Здравствуйте, Sergey G.! Я обратил внимание на ваш профиль и хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

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    Здравствуйте, Clevermindolex! Хочу предложить вам для работы свой проект. Есть готовое решение на Verilog, нужно переделать на VHDL с некоторыми правками

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    Assalam o alaikum !!! I wanna hire an Electronics Engineer with good experience in VHDL coding (ASIC Design). I have a lot of work in the field of ASIC Design and I am looking for an expert who can work on long term basis. I have already talked with few experts but I did not find them suitable for my work.

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    I have a project to write a code using VHDL in ModelSim

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    I have a project to write a code using VHDL in ModelSim

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    I have a project using VHDL in ModelSim

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    I have a code to write on ModelSim using VHDL

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    Modify existing python script to work properly with a specific EEPROM Currently I can read the chip however it is corrupt data, I am assuming the setting are incorrect. Current setup is a Arduino UNO and SPI Flash Programmer script. Task requirement is to fix .py and .ino to work with an ST 25128 SPI EEPROM. If successfl, there will be an additional task to write a script that automates reading and writing to a specific offset.

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    Embedded Systems Imeisha left

    I have a project to write using VHDL on ModelSim

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    VHDL in ModelSim Imeisha left

    I have a project to write on ModelSim using VHDL

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    I am looking for Electronics Engineers with good expertise in VHDL Coding (ASIC Design). I would prefer freelancers from pakistan

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    I have a project using VHDL in ModelSim

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    I have a project to write a code using VHDL on ModelSim

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    I have a project to write a code using VHDL in ModelSim

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    We need someone to help bringup (UBOOT) and build drivers (I2C, SPI, UART, GPIO, customized) and implement modules (ssh, fs, tcp/ip, ethernet, etc). The hardware (based on Zynq®-7000 SoC and FPGA) is ready and some test utilities on PC are ready. The system should use Petalinux distro with all necessary standard libs. The work should be finished in 2 months after awarded. The freelancers should work on-site in Shanghai, China. Please bid if you are ok with above conditions.

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    Ya Eneo
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    I have a code to write on VHDL using ModelSim

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    I have a project to write code using VHDL in ModelSim

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    I have a project to write a code using VHDL in ModelSim

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    I have a project to write using VHDL

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    I have a project using VHDL in ModelSim

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