Verilog / VHDL Kazi na Mashindano
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
Pitia Kazi kwenye Freelancer
| Mradi/Shindano | Maelezo | Zabuni/Wasilisho | Ujuzi | Imeanza | Inaisha | Bei (USD) | |
|---|---|---|---|---|---|---|---|
| verilog project | making verilog on quartus II (cyclone IV) | 9 | Uhandisi, Verilog / VHDL, Software Architecture, Assembly, FPGA | Oct 18, 2017 | Leo6d 18h | $147 | |
| Cloudsim project | I want someone to work on programming part in cloudsim that includes migration, Placement, scheduling and power consumption. | 2 | C Programming, Java, Verilog / VHDL, Software Architecture, Uprogramu C++ | Oct 18, 2017 | Leo6d 7h | $61 | |
| Verilog programming - 18/10/2017 00:34 EDT | Simple verilog programming project. Create an ALU with full [url imeondolewa, ingia kutazama] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. | 7 | Verilog / VHDL | Oct 18, 2017 | Leo6d 6h | $76 | |
| Verification Of Motion Estimator Using UVM | Verification Of Motion Estimator Using UVM(Universal Verification Methodology) | 1 | Verilog / VHDL, Uhandisi wa Umeme, Very-large-scale integration (VLSI) | Oct 17, 2017 | Leo6d 5h | $222 | |
| Verilog programming | Simple verilog programming project. Create an ALU with full [url imeondolewa, ingia kutazama] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. | 5 | Verilog / VHDL | Oct 17, 2017 | Leo6d 2h | $89 | |
| ASIC Design in Verilog | This project is related to Computational Neural Networks | 3 | Matlab na Mathematica, Verilog / VHDL, Neural Networks | Oct 17, 2017 | Oct 17, 20175d 21h | $69 | |
| VHDL Radio clock | everything is going to be explained on the pdf | 11 | Elektroniki, Verilog / VHDL, Microcontroller, Uhandisi wa Umeme, FPGA | Oct 17, 2017 | Oct 17, 20175d 21h | $40 | |
| Design of audio visualiser using DE2-115 Altera board | I want to implement an audio visualizer on the screen of the voice spoken through the mic or played using SD card. | 4 | Verilog / VHDL | Oct 17, 2017 | Oct 17, 20175d 18h | $234 | |
| Matlab power system Simulation using Simulink -- 2 - 17/10/2017 07:15 EDT | My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa | 13 | Uhandisi, Elektroniki, Matlab na Mathematica, Verilog / VHDL, Uhandisi wa Umeme | Oct 17, 2017 | Oct 17, 20175d 13h | $127 | |
| Matlab power system Simulation using Simulink | My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa | 11 | Uhandisi, Elektroniki, Matlab na Mathematica, Verilog / VHDL, Uhandisi wa Umeme | Oct 17, 2017 | Oct 17, 20175d 11h | $145 | |
| Elektroniki, Verilog / VHDL, Microcontroller, Uhandisi wa Umeme, LabVIEW | Oct 16, 2017 | Oct 16, 20175d 5h | |||||
| netlist construction in EE using C++ | refactor the sample code by using the c++ | 9 | C Programming, Verilog / VHDL, Kuprogramu ukitumia C#, Uhandisi wa Umeme, Uprogramu C++ | Oct 16, 2017 | Oct 16, 20174d 18h | $135 | |
| project for Ahmed M -- 2 - 16/10/2017 12:09 EDT | I believe you must do this project. | 2 | Verilog / VHDL | Oct 16, 2017 | Oct 16, 20174d 18h | $127 | |
| project for Ahmed M | I believe you must do this project. | 1 | Verilog / VHDL | Oct 16, 2017 | Oct 16, 20174d 17h | $155 | |
| verilog project | want verilog code on fpga i want soon | 2 | Uhandisi, Verilog / VHDL, Software Architecture, LabVIEW, FPGA | Oct 16, 2017 | Oct 16, 20174d 16h | $8 | |
| ASIC Designs and Development | Hello. I am into a project that involves creating PCB / ASIC design with FPGA/CLPD. The specified ASIC Architecture as a product needs to be able calculate one or more algorithms connected through some type of data socket. Performance and power is important. I am interrested to get in touch with a board designer and vhdl developer that have knowledge both with electrical layouts and vhdl. ... | 6 | Uhandisi, Elektroniki, Verilog / VHDL, Uhandisi wa Umeme, Mpangilio wa PCB | Oct 16, 2017 | Oct 16, 20174d 10h | $15 | |
| veriloghdl code for calculation area | THis must implement on quartus( altera FPGA cyclone IV) | 3 | C Programming, Verilog / VHDL, Microcontroller, Uprogramu C++, FPGA | Oct 16, 2017 | Oct 16, 20174d 9h | $71 | |
| making verlog hdl code | calculataion area in black and white image on fpga ( cyclone IV) | 7 | C Programming, Verilog / VHDL, Microcontroller, Uhandisi wa Umeme, Uprogramu C++ | Oct 16, 2017 | Oct 16, 20174d 6h | $124 | |
| VHDL Coursework | help in VHDL codes ,, everything will be explained later | 11 | Uhandisi, Elektroniki, Verilog / VHDL, Uhandisi wa Umeme | Oct 15, 2017 | Oct 15, 20173d 21h | $56 | |
| fpga software | I want to read programmes in FPGA chips | 17 | C Programming, Verilog / VHDL, Software Architecture, FPGA | Oct 15, 2017 | Oct 15, 20173d 16h | $413 | |
| creation of hardware module using verilog which will be able to communicate with the memory of the processor | using Verilog which will be able to communicate with the memory of the processor | 3 | Verilog / VHDL | Oct 14, 2017 | Oct 14, 20172d 15h | $63 | |
| simple verilog hdl code | calculate each area in black and white image | 10 | C Programming, Uhandisi, Verilog / VHDL, Microcontroller, FPGA | Oct 13, 2017 | Oct 13, 20172d 4h | $41 | |
| Simple Verilog Project | Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3. | 7 | Uhandisi, Matlab na Mathematica, Verilog / VHDL, Uhandisi wa Umeme, FPGA | Oct 13, 2017 | Oct 13, 20171d 21h | $20 | |
| Color space conversions and FPGA's | 3 pages report in two parts on: (i) fundamental information about FPGAs and their programming, and (ii) standard color spaces and formulas for converting those color spaces into other ones. (Plagarism free) finished in 3 days maximum. | 8 | Uhandisi, Verilog / VHDL, Uhandisi wa Umeme, FPGA | Oct 13, 2017 | Oct 13, 20171d 11h | $69 | |
| Build software | Looking for expert in FPGA and verilog | 18 | C Programming, Verilog / VHDL, Software Architecture, Uprogramu C++, FPGA | Oct 12, 2017 | Oct 12, 20176h 25m | $480 | |
| Statcom in simulink Power electronics expert -- 3 | Statcom in simulink Power electronics expert needed | 12 | Elektroniki, Matlab na Mathematica, Verilog / VHDL, Uhandisi wa Umeme, FPGA | Oct 11, 2017 | Oct 11, 2017Imeisha | $260 | |
| Statcom in simulink Power electronics expert -- 2 | Statcom in simulink Power electronics expert needed | 9 | Elektroniki, Matlab na Mathematica, Verilog / VHDL, Uhandisi wa Umeme, FPGA | Oct 11, 2017 | Oct 11, 2017Imeisha | $164 | |
| Want to develop robotic program and test the same with simulation to check feasibility of and automation idea | Existing : Manual labours are lifting filled 25 kg bags from stack of machine palletised load (40 bags per wooden pallet, and loading into trucks, containers. Automation solution : Using three axis gantry robot, vacuum lifting end tool and smart programming to create fully automatic truck loading system. All above only on simulation, 3d models to check feasibility of solutions and then to us... | 5 | Matlab na Mathematica, Verilog / VHDL, Software Architecture, Ujenzi wa Software, Kuprogrammu | Oct 11, 2017 | Oct 11, 2017Imeisha | $4680 | |
| Convert a code from Aptech Gauss language into Matlab with Parallel processing.....!!!! | I have a code written in Aptech Gauss program that I want to convert into Matlab and I want the code to run under CUDA power in Matlab. | 5 | Matlab na Mathematica, Verilog / VHDL, Software Architecture, CUDA, Ujenzi wa Software | Oct 11, 2017 | Oct 11, 2017Imeisha | $121 | |
| VLSI PROJECTS | FIND THE ATTACHED IEEE [url imeondolewa, ingia kutazama] REQUIREMENTS | 4 | Verilog / VHDL, FPGA, Very-large-scale integration (VLSI) | Oct 11, 2017 | Oct 11, 2017Imeisha | $86 | |
| Statcom in simulink Power electronics expert | Statcom in simulink Power electronics expert needed | 9 | Elektroniki, Matlab na Mathematica, Verilog / VHDL, FPGA | Oct 11, 2017 | Oct 11, 2017Imeisha | $114 | |
| Convert a code from Aptech Gauss language into Matlab with Parallel processing. | I have a code written in Aptech Gauss program that I want to convert into Matlab and I want the code to run under CUDA power in Matlab. | 3 | Matlab na Mathematica, Verilog / VHDL, Software Architecture, CUDA, Ujenzi wa Software | Oct 10, 2017 | Oct 10, 2017Imeisha | $153 | |
| Develop, Test and Implement it in software environment and simulate the circuit functionality - open to bidding | We need to develop a digital multiplier circuit and we need to test the circuit design, Implement it in software environment and simulate the circuit functionality. This is going to be part of a bigger project (ARM IP Core, DSP CPU) and we may need to compare the circuit functionality with some other recommended multiplier in terms of speed and foot print. | 7 | Elektroniki, Verilog / VHDL, Uhandisi wa Umeme, Ubunifu wa Digitali, Ubunifu wa Circuit | Oct 10, 2017 | Oct 10, 2017Imeisha | $107 | |
| Prelab | Write VHDL code | 7 | Verilog / VHDL | Oct 10, 2017 | Oct 10, 2017Imeisha | $27 | |
| dimensionality reduction using PCA | we will consider use of PCA for simple dimensionality reduction, i.e., determining the signal subspace when there are more observations than the underlying latent variables—signals. The main assumption here is that both the noise and signals are independent and identically distributed Gaussians, however the the signals are correlated among themselves while the noise components are not, ... | 14 | Matlab na Mathematica, Verilog / VHDL, Uchambuzi wa Elementi Mahususi, CUDA, FPGA | Oct 10, 2017 | Oct 10, 2017Imeisha | $408 | |
| ZYNQ c/ verilog project(s) | There is a Zynq C/ Verilog project involving BRAM and data structures , to be done. We will start with a 50 usd small project, on successful completion we will move into larger budget projects( a few hundred USD ones) .PM me to talk the details. | 11 | C Programming, Verilog / VHDL | Oct 10, 2017 | Oct 10, 2017Imeisha | $82 | |
| Altera DE115 - Audio signal processing | Record voice , Add and Remove Noise and play back recording. Design and implement the verilog code on an Altera DE2-115 Development Board. Available Hardware Microphones, Speakers | 9 | Verilog / VHDL, Microcontroller, Software Iliyopachikwa, Assembly, FPGA | Oct 10, 2017 | Oct 10, 2017Imeisha | $226 | |
| Audio Signal Processing | AIM - Record Audio , Add and Remove Noise and play back audio. To design and implement the Embedded System centred on an Altera DE2-115 Development Board. The project should be based on a Verilog HDL implementation. Available Hardware In addition to the DE2-115 board, the following hardware devices are available. If you wish to do a project requiring hardware support but don’t see the... | 7 | Verilog / VHDL, Microcontroller, Uhandisi wa Umeme, Software Iliyopachikwa, FPGA | Oct 10, 2017 | Oct 10, 2017Imeisha | $509 | |
| Sequence Diagram | There is a service class called PurchaseOrder that is called when a customer makes a purchase. It has a public method purchase(Account, Order). It does the following. a. Call [url imeondolewa, ingia kutazama]() b. Call [url imeondolewa, ingia kutazama](Account) c. Call [url imeondolewa, ingia kutazama]() d. [url imeondolewa, ingia kutazama]() calls [url imeondolewa, ingia kutazama](amount) whi... | 6 | Verilog / VHDL, Software Architecture, PLC & SCADA, Uchambuzi wa Elementi Mahususi, Uhandisi wa Kuchora | Oct 10, 2017 | Oct 10, 2017Imeisha | $37 | |
| Matlab Program for Harmonics Analysis for a sampled data (Data in excel format) | Need a Matlab program to perform Harmonics Analysis for a sampled data (data in Excel format). Matlab Codes must structured to read data from Excel file. Please find the attached Excel file [url imeondolewa, ingia kutazama] | 22 | Excel, Matlab na Mathematica, Verilog / VHDL, Software Architecture, Ujenzi wa Software | Oct 7, 2017 | Oct 7, 2017Imeisha | $22 | |
| UML/MARTE modeling | I want to build an interface(which consists of rules) to transform any MML model to a UML-MARTE model using AGG(algebraic graph transformation). | 1 | Verilog / VHDL, Kutengeneza UML, Uchambuzi wa Elementi Mahususi, SAS, CATIA | Oct 7, 2017 | Oct 7, 2017Imeisha | $587 | |
| matlab report making 10 pages minimum | hi discussion via chat no front milestone need it in 12 hrs 10 mages maximum paper should be in IEEE formats no plagiarism is there.. please give a good quote | 10 | Matlab na Mathematica, Verilog / VHDL, LaTeX, Hisabati, Fizikia | Oct 7, 2017 | Oct 7, 2017Imeisha | $48 | |
| Matlab Write a Function for Forward Kinematics of the RPR Robot | Input Format are the joint angles in radian, as shown in the figure is the extension of the prismatic joint in inches, as shown in the figure Output Format R is a 3x3 rotation matrix representing (Note: where represents a point in frame x) pos is a 4x3 matrix where each row contains the x,y,z coordinates represented as [x y z] in matrix form. Each row is the x,y,z coordinates of a point... | 16 | Matlab na Mathematica, Verilog / VHDL, Software Architecture, Uchambuzi wa Elementi Mahususi, Ujenzi wa Software | Oct 7, 2017 | Oct 7, 2017Imeisha | $38 | |
| String compare algorithm | need an algorithm that would compare two long strings delimited by | | 3 | Matlab na Mathematica, Verilog / VHDL, Algorithm, CUDA, Mafunzo ya Mashine | Oct 7, 2017 | Oct 7, 2017Imeisha | $1960 | |
| Cryptoanalysis - Cryptograpgy - C programming | I am looking for someone to write me a code in c that will test the cryptographic strength of the passwords. I can share more specific instructions and dummy passwords. I need a simple program. | 9 | C Programming, Verilog / VHDL, Software Architecture, Prolog, Uprogramu C++ | Oct 6, 2017 | Oct 6, 2017Imeisha | $69 | |
| MSF and DCF receiver | everything will me explained later | 5 | Uhandisi, Elektroniki, Verilog / VHDL, Uhandisi wa Umeme, Binary Analysis | Oct 6, 2017 | Oct 6, 2017Imeisha | $46 | |
| Embedded Control System Design | It is a project on Embedded Control System Design. I will give the details later. | 12 | C Programming, Verilog / VHDL | Oct 6, 2017 | Oct 6, 2017Imeisha | $44 | |
| ABAQUS Model (CFRP Beam) | I need to make the results of this ABAQUS model converge with the experimental data curve (shown in the Excel sheet: Load vs Deflection). The current results shows a much higher yield and peak loading compared to the experimental data. The model files are attached to this project. | 13 | Verilog / VHDL, Uchambuzi wa Elementi Mahususi, Michoro ya Kompyuta, Uhandisi wa Viwanda, CATIA | Oct 5, 2017 | Oct 5, 2017Imeisha | $189 | |
| Simulation profile | need a private tutor for ANSYS-Fluent and ICEM-CFD | 8 | Matlab na Mathematica, Verilog / VHDL, Uchambuzi wa Elementi Mahususi, FPGA, CATIA | Oct 5, 2017 | Oct 5, 2017Imeisha | $161 | |
| VHDL circuits project | have few questions on digital circuits that I need help with. will provide more details of interested | 23 | Verilog / VHDL, Ubunifu wa Circuit, Kuprogrammu | Oct 4, 2017 | Oct 4, 2017Imeisha | $77 |
Showing 1 to 50 of 114 entries