Verilog / VHDL jobs

Nataka Kuajiri Nataka Kufanya Kazi

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Ajiri Verilog / VHDL Designers

6 kazi zimepatikana, bei imeletwa USD

LabVIEW Controls Program 6 siku left

I work for a company that builds Air Cooled Heat Exchangers. We pressure test all of our units before they leave the plant to ensure they hold pressure without any leaks. To improve safety, we are going to a fully automated test system, which is to be controlled by a DAQ system using a Laptop. I am looking for someone to write me two separate (but very similar) LabView programs for both of the te...

$3852 (Avg Bid)

$3852 Wastani wa Zabuni

23 zabuni

Zabunia sasa

aurdino project 5 siku left

Build a robot connecting circuits and programming

Uhandisi wa Umeme Elektroniki Uhandisi Microcontroller Verilog / VHDL

$1059 (Avg Bid)

$1059 Wastani wa Zabuni

25 zabuni

Zabunia sasa

H.264/H.265 decoder 4 siku left

The project is to design a video decoder for H.264/265 in ASIC design Performance requirement 1080p30 x 8 channels

FPGA Verilog / VHDL

$4518 (Avg Bid)

$4518 Wastani wa Zabuni

9 zabuni

Zabunia sasa

Програмування ПЛІС VHDL/Verilog 3 siku left

Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

Uhandisi wa Umeme Uhandisi FPGA Microcontroller Verilog / VHDL

$390 (Avg Bid)

$390 Wastani wa Zabuni

3 zabuni

Zabunia sasa

DMA controller for AXI4 3 siku left

This project is to design a DMA engine for the AMBA4 system. The engine has one 512b AXI4 master and one 32b AXI4-lite configuration interface. The engine supports following DMA mode: • 1D mode: Single continuous block • 2D mode: multiple continuous blocks equally spaced. • 3D mode: multiple 2D block equally spaced. • Interleaving mode: read multiple blocks and send out interl...

Verilog / VHDL

$509 (Avg Bid)

$509 Wastani wa Zabuni

10 zabuni

Zabunia sasa

RF telecommunication receiver system 2 siku left

Design and simulate a typical RF Telecommunication receiver system IN SIMULINK/MATLAB/LABVIEW

Uhandisi wa Umeme Uhandisi LabVIEW Matlab na Mathematica Verilog / VHDL

$155 (Avg Bid)

$155 Wastani wa Zabuni

32 zabuni

Zabunia sasa

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