Logo ya FreelancerJinsi inavyofanya KaziVinjari Kazi
Ingia Jisajili
Chapisha Mradi
TALII
Circuit Design
Electrical Engineering
Matlab and Mathematica
Translation
Verilog / VHDL
Picha ya jalada la wasifu
Sasa unafuata
Hitilafu katika kufuata mtumiaji.
Mtumiaji huyu haruhusu watumiaji kumfuata.
Tayari unamfuata mtumiaji huyu.
Mpango wako wa uanachama unaruhusu tu ufautiliaji 0. Boresha hapa.
Umefaulu kuacha kufuata
Hitilafu wakati wa kuacha kumfuata mtumiaji.
Umefaulu kupendekeza
Hitilafu katika kumpendekeza mtumiaji
Hitilafu fulani imetokea. Tafadhali onyesha upya ukurasa na ujaribu tena.
Barua pepe imethibitishwa kwa ufanisi.
Picha ya Mtumiaji
$5 USD / saa
Bedera ya VIETNAM
da nang, vietnam
$5 USD / saa
Ni saa 3:58 PM hapa
Alijiunga Aprili 26, 2019
0 Mapendekezo

Duc Nhan L.

@ducnhan11dt3

 5.0 (1 hakiki)
3.5
3.5
100%
100%
$5 USD / saa
Bedera ya VIETNAM
da nang, vietnam
$5 USD / saa
100%
Kazi Zilizokamilika
100%
Kwa Bajeti
100%
Kwa wakati
N/A
Kiwango cha Kuajiriwa Tena

Digital ASIC Engineer

I have 5+ experiences in ASIC design flow, especially Logic design (Verilog/VHDL), Physical Design (PnR, Physical verification) and familiar with many platform from Cadence, Synopsys and Mentor Graphics.
Freelancer Electrical Engineers Vietnam
Angalia woteElectrical Engineers in Vietnam

Wasiliana na Duc Nhan L. kuhusu kazi yako

Ingia ili kujadili maelezo yoyote kwenye gumzo.

Kaguzi

Mabadiliko yamehifadhiwa
Inaonyesha 1 - 1 kutoka kwa 1 - hakiki
 Chuja hakiki kulingana na:
5.0
$550.00 USD
Project 32381403 has been deleted
Thank you so much Nhan!
K
Bedera ya Kyuwon C.
@kwchoi
•
2 years ago

Uzoefu

Logic Design Engineer

Ampere
Apr 2022 - Sasa
- RTL design engineer.

Sr Design Engineer

Cadence Design Systems
Jul 2020 - Apr 2022 (1 year, 9 months)
- In charge as backend engineer (PnR and SI/PI) in design service team. - Participate some customer projects as block owner and chip top. - Build and optimize flow by using perl, python, tcl scripts.

Master Student

ICAT Laboratory - Chungbuk National University
Mac 2018 - Feb 2020 (1 year, 11 months)
- Research hardware cryptography based Physical Unclonable Functions (PUFs) in information security. - Implement many algorithm include encryption/decryption, hash function and integrated with other circuit for fully protocol in information security. - Design an security IP from concept to RTL, synthesis, PnR, physical verification and tape-out.

Elimu

Master

Chungbuk National University, Korea, Republic of 2018 - 2020
(2 years)

Bachelor

Truòng Dai hoc Bách Khoa Da Nang, Vietnam 2011 - 2016
(5 years)

Wasiliana na Duc Nhan L. kuhusu kazi yako

Ingia ili kujadili maelezo yoyote kwenye gumzo.

Udhibitisho

Wafanyakazi Huru Wanaopendelewa
Amedhibitishwa Kiutambulisho
Amedhibitishwa Kimalipo
Amedhibitishwa Kisimu
Amedhibitishwa Kibarua pepe
Facebook Imeunganishwa

Ujuzi wa Juu

Electrical Engineering 1
Circuit Design 1
Translation
Matlab and Mathematica
Verilog / VHDL

Angalia Wafanyakazi Huru sawia:

Electrical Engineers in Vietnam
Electrical Engineers
Circuit Designers
Translators

Pitia Onyesho Sawia

Electrical Engineering
Circuit Design
Translation
Matlab and Mathematica
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