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Picha ya Mtumiaji
$15 USD / saa
Bedera ya INDIA
delhi, india
$15 USD / saa
Ni saa 7:46 PM hapa
Alijiunga Novemba 2, 2015
1 Pendekezo

Punam S.

@punamsengupta

 4.8 (13 hakiki)
3.8
3.8
100%
100%
$15 USD / saa
Bedera ya INDIA
delhi, india
$15 USD / saa
85%
Kazi Zilizokamilika
100%
Kwa Bajeti
56%
Kwa wakati
20%
Kiwango cha Kuajiriwa Tena

ASIC Design and Verification Engineer

Total experience of 7 years into Semiconductor and EDA Industry. Throughout experience in module level RTL coding , verification of ASIC designs and VIP Development. 4+ years of experience in constrained random based Functional verification in front end ASIC flow. Well conversed with verification methodologies such as OVM, UVM for more effective and re-usable test bench component knowledge and familiarity of Functional coverage concepts and System Verilog with APB, I2C, OCP, IOSF, JTAG and USB protocols. Assets as a freelancer: 1. Highly motivated to work on my own. 2. Effective and detailed Communication skill. 3. Ability to learn new technology rapidly, work flexibly and take new initiatives. Technical Exposure: 1. Good expertise in C++ programming language. 2. Very Good expertise in verilog and system verilog languages. 3. Good knowledge of Perl scripting. 4. Good expertise in OVM and UVM methodologies.
Freelancer Verilog / VHDL Designers India
Angalia woteVerilog / VHDL Designers in India

Wasiliana na Punam S. kuhusu kazi yako

Ingia ili kujadili maelezo yoyote kwenye gumzo.

Kaguzi

Mabadiliko yamehifadhiwa
Inaonyesha 1 - 5 kutoka kwa 13 - hakiki
 Chuja hakiki kulingana na:
0.0
$135.00 USD
AES Encryption/Description with SHA256 key for zedboard
The project is not completed according to the dispute
Verilog / VHDL
FPGA
R
Bedera ya Jean C.
@remix224
•
7 years ago
5.0
$60.00 USD
Writing a verification plan for a Design under test in system verilog -- Project for punamsengupta
My go-to freelancer for anything related to VLSI projects.I had an urgent requirement on this and she delivered this in few hours which is amazing. She is an experienced person and technically very sound. She always delivers before time and makes sure everything is as per requirements and always exceeds the expectations. Will hire her again .
Verilog / VHDL
Picha ya Mtumiaji
Bedera ya Rossyr R.
@jonathanrossy
•
7 years ago
0.0
$30.00 USD
FPGA Implementation
The project is not completed according to the dispute
C Programming
Verilog / VHDL
OpenCL
Picha ya Mtumiaji
Bedera ya Led R.
@myworldvw
•
7 years ago
4.6
$100.00 AUD
Project on VeriLog
She is a good asset.
Verilog / VHDL
Electrical Engineering
S
Bedera ya Shiv R.
@shivratan84
•
8 years ago
4.6
$350.00 USD
Verilog Implementation of Pipelined Execution of Windowed Image Computations
Punam is very well versed with Verilog coding. She has a good understanding of digital logic as well. She delivered a very quality code to me. My suggestions for code changes were very well taken. She took extra effort on some days to debug the code to implement exactly what I wanted. I would recommend anybody to hire Punam, for the knowledge she has in digital design.
Perl
Verilog / VHDL
FPGA
A
Bedera ya Aswin V.
@aswinvijayavarma
•
8 years ago

Uzoefu

Senior Verification Engineer-I

Microchip technology
Apr 2013 - Apr 2015 (2 years)
Project : USB 2.0 Block level verification.

R&D Engineer-II

Synopsys India Pvt. Ltd.
Jul 2012 - Mac 2013 (8 months, 1 day)
Project : AMBA APB VIP Development .

Senior Project Engineer

Wipro Technologies
Jun 2008 - Jun 2012 (4 years)
Project 1 : Modular PHY DFX Verification. Project 2: Verification of IOSF2OCP Bridge.

Elimu

M.Tech (VLSI)

India 2006 - 2008
(2 years)

B.E (Instrumentation and control engineering)

Saurashtra University, India 2001 - 2005
(4 years)

Wasiliana na Punam S. kuhusu kazi yako

Ingia ili kujadili maelezo yoyote kwenye gumzo.

Udhibitisho

Wafanyakazi Huru Wanaopendelewa
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Ujuzi wa Juu

Verilog / VHDL 11
Electronics 3
FPGA 3
Report Writing 1
Electrical Engineering 1

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