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$5 USD / saa
Bedera ya PAKISTAN
rawalpindi, pakistan
$5 USD / saa
Ni saa 7:06 PM hapa
Alijiunga Oktoba 15, 2011
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Elecguru011

@Elecguru011

0.0 (1 hakiki)
0.0
0.0
83%
83%
$5 USD / saa
Bedera ya PAKISTAN
rawalpindi, pakistan
$5 USD / saa
N/A
Kazi Zilizokamilika
N/A
Kwa Bajeti
N/A
Kwa wakati
N/A
Kiwango cha Kuajiriwa Tena

Embedded Design Enigneer with expertise in FPGA and DSP Systems Engineering

I specialize in Field Programmable Gate Array design , I have developed numerous VHDL/Verilog ip cores that have been integrated in high performance embedded systems, Nios SOC , ARM SOC, Digital Signal Processing and Image Processing. I also have extensive experience in test and verification of FPGA designs using Tcl and VHDL/Verilog Testbenches. Multilayer PCB design is also my expertize. #PLEASE IGNORE COMMENTS FROM "Mohammad.K" linked to Wishbone bus . He dealt the project work unprofessionally and used very pathetic language. After setting a milestone he demanded/begged for incomplete report before delivery date and criticized me for not delivering as promised. He is very difficult person to work with and it is very confusing and hard to understand his communication.

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Ingia ili kujadili maelezo yoyote kwenye gumzo.

Portfolio

2061093
2060586
1874656
1853254
1853244
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2061093
2060586
1874656
1853254
1853244
1629242

Kaguzi

Mabadiliko yamehifadhiwa
Inaonyesha 1 - 1 kutoka kwa 1 - hakiki
Chuja hakiki kulingana na:
1.0
$50.00 USD
He is a real rascal. Do not pay this buttered before he delivers. he dose not know nothing will grab money from you and will not even than replay. Do not release the milestone whatever they say.
Verilog / VHDL
FPGA
Picha ya Mtumiaji
Bedera ya Muhammad K.
@nasirkhanpak25
•
7 years ago

Uzoefu

Project Engineer

Embedded Strings pvt ltd
Jul 2015 - Sasa
Embedded Systems design , FPGA and PIC Microcontroller based hardware design . Firmware and Software design and Systems analysis using Matlab.

Team Lead

NUST SEECS
Jan 2012 - Des 2014 (2 years, 11 months)
I worked as Hardware Design group Team Lead , developed modules for wireless sensor network.

Digital and Analogue Design Engineer

COM DEV
Mei 2010 - Des 2011 (1 year, 7 months)
FPGA Hardware Design of Satellite Communication system.

Elimu

M.Sc Telecommunication Engineering

Preston University, Pakistan 2015 - 2017
(2 years)

MSc Electronics Engineering

Staffordshire University, United Kingdom 1998 - 2001
(3 years)

Sifa

DSP Systems Engineering

University of California , Irvine
2012
Digital Signal Processing fundamentals, DFT,FFT , Digital Filter modelling and simulation using Matlab, FIR and IIR filter implementation on FPGA

Winner Best Design

Cypress Semiconductor
2004
Reconfigurable Logic using PSOC

Chapisho

OTDR Implementation on FPGA

Embedded Strings (pvt)Ltd
Optical Time Domain Reflectrometery In optical fiber communication, optical time domain reflectometery (OTDR) is a commonly used technique for characterization and fault location of optical fiber transmission systems. It involves measuring the fraction of a probe pulse that is scattered back (by Rayleigh scattering) from a silica fiber. Because of the very small levels of backscatter in single-mode fiber at long wavelengths, very sensitive optical detection is necessary to achieve adequate range performa

Audio Signal Processing

Ahmed A Ghouri
An audio signal frequency range is from 20Hz to 20Khz. In a music sample 20Khz bandwidth is required to encompass all harmonics. Although natural sounding speech only requires about 3.2Khz . Telecommunication systems typically operate with a sampling rate of about 8 kHz, allowing natural sounding speech, but greatly reduced music quality. Here we are proposing a FPGA based audio signal filtering system which is reconfigurable and can be used as a Processing Engine to reduce background noise from a musi

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