VHDL simple fixes
$10-30 USD
Kulipwa wakati wa kujifungua
Hi I have a VHDL project which synthesizes, but it has some simple errors when simulating (unconnected signals mainly).
I need someone who can fix it and run a simulation to identify one issue.
Kitambulisho cha Mradi: #27583321
Kuhusu mradi
12 wafanyakazi huru wanazabuni wastani wa $22 kwa kazi hii
I have extensive knowledge on vhdl and digital design Drop a line over chat for any questions you might have Best regards
Hi, I am Mtech graduate from IIT Roorkee and working on Hardware Description Languages Verilog and VHDL for the past 3 years. I have done many Digital system design projects using RTL design and FSM and had a working e Zaidi
Dear Mr/Ms, I am an electronic engineer with more than 5 years of experience. I have an advanced knowledge on VHDL programming over Xilinx and Altera FPGA. Check my skills. Hope we can work together. Regards, Ju Zaidi
I am interested in your project. Is it possible to discuss the project details? If you can provide information about the details, we can proceed faster. what program do you use quartus or something else
hi, i have experince in understnading other person codes and fixing issues with verilog and VHDL. i will be able to do this in a matter on minutes. i have expertise in verilog and VHDL. i will be using Xylinx produ Zaidi
Hello! I can help you for your problem! I have 5 years experience whith practice vhdl. It is my first work in this platfotm. I hope it will be successfully! Thanks
Hi, I have 3 years experience and worked on complex hardware projects and create module from the scratch. Hope to help you on the issue