Project goal is designing 4x4 binary multiplier with shift & add algorithm.
Stricted rules: Project must be prepared with Verilog [Vivado Design Suite] (System Verilog and VHDL is not acceptable)
I need circuit design, Verilog models and basic report (Explanation of how things work, schematics, verilog codes etc)
If you're interested, I can share detailed pdf of project with you.
Hi
I have been working on Verilog-VHDL and Xilinx and Altera FPGAs by more than 6 years.
I have done the similar project already. Please let me know if the requirement is still there I can work on it.
Thanks
Hi Dear, Hope you are doing well,
I can do your this work. Please tell me which binary shift algorithm you have to use and do you also need to consider Q formatting? I am also working on Xilinx Vivado and I can do your this work. Please come in chat to discuss in details and let me know which board you have to use?
Regards
Abdul Rehman
Hi, glad to bid on your project.
I’m an expert on VLSI with VHDL , Verilog , spice , system Verilog.
I want to discuss the project further with you.I have experience in this job, waiting for a reply from your side thanks.
Hello there,
I am an Electrical & Electronics Engineer by profession and specialist in FPGA designing by using verilog/VHDL.
I have been doing such tasks on different freelancing platforms.I have read your task details and i am pretty sure i can do this in a professional manner.
My recent project was the implementation of 3-bit Arithmetic Logic Unit by using Vivado software.
If you will have any questions you can ask me.
Looking forward to hearing from you
Regards
Waqar Shahzad
I know the design of 4*4 binary multiplier and I have recently learnt Verilog. I can start working on it as soon as possible. I can send the Circuit design of the multiplier the instant you contact me, and writing codes and the report will be done within a week.
I have been working on PUF based security project using FPGA since 2018. I mostly work on Xilinx FPGA (Verilog as programming language). I have recent publication in IEEE-SOCC 2019. Looking for positive reply !!
I am a FPGA design engineer and this is pretty basic stuff. I have already worked on multiplier. so i can finish this project. ping me if ur interested. I can provide u the verilog modules and ciruit design.
Hey man! I am your life vest. I am an Electrical and Electronics Engineering Student and what you are asking is easy-peasy. You have my word, your project is going to be great. I am waiting for your message to discuss details.