FPGA4student

£20-250 GBP

Imefungwa

Imechapishwa

over 2 years ago

£20-250 GBP

Kulipwa wakati wa kufikishwa

This VHDL project is to design and implement noise filtering, metastabiliy and synchronization of given signals

Verilog / VHDL

Electrical Engineering

FPGA

Engineering

Kitambulisho cha mradi: 32292298

Kuhusu mradi

5 mapendekezo

Mradi wa mbali

Inatumika 2 yrs ago

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Barua pepe

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Eleza pendekezo lako

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5 wafanyakazi huru wana zabuni kwa wastani £162 GBP kwa kazi hii

@KolaPeters

Hi there, i have thoroughly gone through your project description, i'm an expert in this., I can help you in your project, please kindly send me a message. I'm a senior engineer with rich experience in Engineering, Matlab and Mathematica, Verilog / VHDL, Electrical Engineering, FPGA. I am a Python developer with 5+ years of experience Skills: PyQt, PySide/PyQt,Scrapy, BeautifulSoup Java, C++, C#, SQL, 4, Pillow, Matplotlib, Xml, PHP, Django json, and csv modules. Expert in statistical analysis of datasets/images and apply ML/DL algorithm with python (Tensorflow, Keras,Pytorch) and R. I am interested in taking this task up for you and I hope I could awake your interest in me. Please kindly send me a message in chat window for more about the project and to adjust price, note price quoted in bid is not the final price, it can be less or more after discussing the project. I am always online, work hard and very sensitive to details. I hope to read from you in chat box. Best regards

£200 GBP ndani ya siku 5

4.7

(7 hakiki)

4.3

@AmidKhatibi

Hello, I have read the project description carefully and based on my 5+ years experience, I can do this job very well. Don't hesitate to check out my portfolio: https://www.freelancer.com/u/AmidKhatibi Kindly drop a message so that we can discuss. Best regards, Amid

£150 GBP ndani ya siku 5