Verification IP development for AXI Protocol using system Verilog

Imefungwa Ilichapishwa Miaka 6 iliyopita Kulipwa wakati wa kujifungua
Imefungwa Kulipwa wakati wa kujifungua

VIP component development for AXI3.0 protocol with support for various features like burst type, burst size, protection, out of order, overlapping, aligned,WRAP,fixed burst . Develop BFM, Generator, Monitor, and Coverage models and also the slave model.

C Programming Uprogramu C++ FPGA Software Architecture Verilog / VHDL

Kitambulisho cha Mradi: #15529477

Kuhusu mradi

3 mapendekezo Mradi wa mbali Ipo mtandaoni %project.latestActivity_relativeTime|badilisha%

3 wafanyakazi huru wanazabuni wastani wa ₹11296 kwa kazi hii

raulbehl

Hello! Please check my profile and reviews to know a bit about me and my work. Hope you would contact to discuss further. Thank you! Relevant Skills and Experience Verilog - 3+ years AXI Protocol - 2+ years SV/UVM - 2 Zaidi

₹13888 INR kwa siku 15
(Maoni 118)
6.4
amitkum1

I'll create VIP for AXI with master and slave modes in constrained verification random environment. If UVM is ok, i'll base that testbenc on UVM. Relevant Skills and Experience Expert System verilog knowledege, many y Zaidi

₹7777 INR kwa siku 5
(Maoni 0)
0.0
honesthiren

I would be able to finish this proficiently as I have know this protocol well and my current project also involves this project. Relevant Skills and Experience I am working as a Sr. ASIC Verification Engineer in one o Zaidi

₹12222 INR kwa siku 15
(Maoni 0)
0.0