Codec implementation

₹12500-37500 INR

Imefungwa

Imechapishwa

over 2 years ago

₹12500-37500 INR

Kulipwa wakati wa kufikishwa

Implement the video codec work flow which is simulated in the vivado on the Zync board

FPGA

Verilog / VHDL

C Programming

Kitambulisho cha mradi: 32296001

Kuhusu mradi

3 mapendekezo

Mradi wa mbali

Inatumika 2 yrs ago

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@fliudmyla1

Hi, Dear I`ve read your project post very carefully and I`m really interest in your project. I`ve rich 6+years of experience and knowledge in video codec with directshow and ffmpeg. If you hire me, I can start right now and I`ll provide you with the best results to your satisfaction. I have the ability to do that. I would like to discuss more regarding project via chat. Please invite me to chatbox. Thanks for reading my proposal.

₹37,500 INR ndani ya siku 7

5.0

(1 hakiki)

2.1

@geethageetu

Hi Client, I Have experince in Vlsi design and Veriffication using Verilog and VHDL,I am and My Team working on Diffrent tools like Xilinx,Vivado,Model sim,ect..... Working on diffrent FPGA'S like Basys 3,Artix7, Spartan6,ect........ So I am sure I will definitely give the support to your project,If you want more discussion you can freely text to me. Thank you.

₹37,000 INR ndani ya siku 15