Simple Verilog Project

$15 USD

Imefungwa

Imechapishwa

over 6 years ago

$15 USD

Kulipwa wakati wa kufikishwa

Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3.

Electrical Engineering

Engineering

FPGA

Matlab and Mathematica

Verilog / VHDL

Kitambulisho cha mradi: 15393347

Kuhusu mradi

7 mapendekezo

Mradi wa mbali

Inatumika 6 yrs ago

Unatafuta kupata pesa?

Barua pepe

Faida za kutoa zabuni kwenye Freelancer

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Eleza pendekezo lako

Ni bure kujiandikisha na kutoa zabuni kwa kazi

7 wafanyakazi huru wana zabuni kwa wastani $25 USD kwa kazi hii

@loi09dt1

A proposal has not yet been provided

$30 USD ndani ya siku 1

4.8

(131 hakiki)

6.7

@raulbehl

Hey! Please check my reviews and profile to know more about me and my work. Thank you!

$20 USD ndani ya siku 4

5.0

(58 hakiki)

5.8

@iZoneFreelancer

Have worked on similar projects using VHDL & Verilog. So, can do it. Relevant Skills and Experience Relevant Skills: 1. Verilog & VHDL Proposed Milestones $50 USD - Completion More details about the requirement.

$50 USD ndani ya siku 10

3.5

(4 hakiki)

2.9

@prakashddit

have 3+ years of expertise

$20 USD ndani ya siku 1

4.6

(2 hakiki)

2.0

@davidkarani

I request for this job humbly and i will do it on time

$20 USD ndani ya siku 3

0.0

(0 hakiki)

0.0

@Ramvenkat111

Hai, I have 4 years of experience in FPGA design and validation. Handled complex projects on image processing and signal processing. Feel free to contact any time. Thankyou.

$20 USD ndani ya siku 10