Phase 1: Feasibility study - porting Micropython to RISC V SoC running on Arty A7 35T FPGA board with support for makecode editor.

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Imefungwa Kulipwa wakati wa kujifungua

Hi,

I need some help with an initial detailed feasibility study on how to Port Micropython onto an open-source RISC V SoC ( i will send you the exact CPU implementation at a later stage) running on Arty A7 35T FPGA board and how much work is involved with a detailed task list and an estimated timescale.

The projects end goal is to build RISC V porting with all the GPIO & peripherals working in Micropython and the implementation should be compatible with Micropython makecode editor( [login to view URL]).

The final objective of this project is to create an open-source Micropython RISC V board with all the required IO functions and support for the makecode editor using USB port.

A similar RISC V Micropython porting like in these repos creaeted by Miodrag Milanović in GitHub.

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Some additional info:

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Regards,

Prathap

Software Iliyopachikwa Ubunifu wa Circuit Python Microcontroller Uprogramu C++

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KolaPeters

Note: I will build a RISC V porting with all the GPIO & peripherals that is working in Micropython and the implementation wouldbe compatible with Micropython makecode. Thanks for your job posting. As an electrical eng Zaidi

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Shone15Paul

AN EXPERT IN ABOVE NAMED SKILLS, DEAR CLIENT, After KEENLY and PROFESSIONALLY reading your description and being able to comprehend CLEARLY with Mentioned REQUIRED SKILLS, and possessing the aforementioned QUALIFICATIO Zaidi

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