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VHDL - Design Programming and Simulation Test Bench

€8-30 EUR

Imefungwa
Imechapishwa about 5 years ago

€8-30 EUR

Kulipwa wakati wa kufikishwa
General Information “Counter Unit”, “IO Control Unit”, “Top Level & Testbench” and “Synthesis & Implementation will give you additional information about each sub-module of the project in order to realize the counter. FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Basys3 FPGA development board. The FPGA used is a Xilinx Artix-7 FPGA (XC7A35T-1CPG236C). An asynchronous high-active reset shall be used to initialize the design (BTNC button on the Basys3 board). The whole design uses a 100 MHz clock. One switch for the selection of the count direction (CNT_UP/CNT_DOWN). ‘1’ … count up, ‘0’ … count down. If the counter reaches the maximum value (minimum value in case of count down) it continues counting at the minimum value (maximum value in case of count down). One switch for holding the counter (CNT_HOLD) ‘1’ … hold, ‘0’ … normal operation. One switch for resetting the counter (CNT_RESET) ‘1’ … reset, ‘0’ … normal operation The priorities for these switches are: 1. reset 2. hold 3. count direction The counting mode (decimal, hexadecimal, or octal) and the counting frequency of the least significant digit (1 Hz, 10 Hz, 100 Hz, or 1000 Hz) depend on your number in the attendance list as shown in Table 1 (if you work in groups, use the number of the group member with the lowest number). All four digits of the counter have to count at the same clock edge, this has to be proven by simulation.
Kitambulisho cha mradi: 18740058

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7 mapendekezo
Mradi wa mbali
Inatumika 5 yrs ago

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7 wafanyakazi huru wana zabuni kwa wastani €46 EUR kwa kazi hii
Picha ya Mtumiaji
Dear sir I have more than 10 years experience in digital design using vhdl and I already have the Basys3 board, please check my profile also please message me so that we can discuss
€29 EUR ndani ya siku 1
4.9 (472 hakiki)
8.0
8.0
Picha ya Mtumiaji
i have expertise in FPGA since 3+ years. Let's discuss in more detail. life time support will be provided.
€34 EUR ndani ya siku 1
4.8 (7 hakiki)
3.6
3.6
Picha ya Mtumiaji
Hi Sir, We Rogtech having 5 years of experience in Verilog and VHDL programming. Your project description matches with our expertise and it is proven in Modelsim Simulation. Looking forward to discuss with you in detail. Please ping us immediately we are happy to deliver the project. Thanks and Regards Rogtech
€111 EUR ndani ya siku 1
5.0 (2 hakiki)
1.6
1.6
Picha ya Mtumiaji
Very similar of a homework done by my students. We also use Basys 3 board. The work will be well done but you will not learn anything.
€50 EUR ndani ya siku 1
0.0 (0 hakiki)
0.0
0.0
Picha ya Mtumiaji
I'm an experienced FPGA design engineer. I'm interested and willing to work with you. Let's discuss more
€29 EUR ndani ya siku 2
0.0 (0 hakiki)
0.0
0.0
Picha ya Mtumiaji
I have done similar project in the past. It seems like a course project and it is quite simple actually.
€39 EUR ndani ya siku 2
0.0 (0 hakiki)
0.0
0.0

Kuhusu mteja

Bedera ya AUSTRIA
Vienna, Austria
0.0
0
Mwanachama tangu Feb 13, 2019

Uthibitishaji wa Mteja

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