finding sinad of adc using cadence -- 2

I need to verify the dynamic specifications of an analog-to-digital converter (ADC) simulated using cadence vitruoso software. Firstly, I need to verify the ideal circuit from the library before using it in my design. I used an 8-bit ideal ADC followed by an ideal DAC, both extracted from the ahdl library. My input is a sinusoidal signal with the following specifications (offset = 0.6V, Vpeak = 0.3V, input frequency = 500KHz) and my clock is a pulsed wave signal with 50MHz as the sampling frequency. From the output, I have plotted the discrete Fourier transform. Ideally, an 8-bit ADC should have a signal-to-noise ratio of 49.92 [sinad = 6.02*8 + 1.76; where 8 is the effective number of bits]. However, all my tests result in a much smaller sinad. After finding the appropriate sinad for the ideal case, I need to find the sinad for my design.