DDR SD ram controller

₹12500-37500 INR

Imefungwa

Imechapishwa

over 6 years ago

₹12500-37500 INR

Kulipwa wakati wa kufikishwa

DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero

Electrical Engineering

Kitambulisho cha mradi: 15826487

Kuhusu mradi

8 mapendekezo

Mradi wa mbali

Inatumika 6 yrs ago

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8 wafanyakazi huru wana zabuni kwa wastani ₹27,291 INR kwa kazi hii

@hungfreelancer

I have 10 years of experiences in design and verify using Verilog and SystemVerilog HDL. I have experience of using DE1, DE2 (Altera), Virtex7(Xillinx),.. Please choose me. Best Regards. Relevant Skills and Experience Verilog, SystemVerilog, Quartus II, Vivado, VCS Synopsys, design and verify FLASH,SRAM,SDRAM,DDR2 memory controller. Proposed Milestones ₹2000 INR - Accept Award Project ₹13555 INR - Release

₹15,555 INR ndani ya siku 10

5.0

(8 hakiki)

4.2

@eopskzs

DDR controller core will be generated for selected Xilinx FPGAs as requested in project description. A report will than be generated and simulation results will be shown in ModelSIM. Relevant Skills and Experience Xilinx FPGAs VHDL Digital Design Proposed Milestones ₹25000 INR - Design and delivery of the system Which FPGA product/products are you targeting for this study?

₹25,000 INR ndani ya siku 12

5.0

(6 hakiki)

4.1

@alinayyar

Dear, We will use xilinx and verilog for coding purposes. We will give RS-232 interface for sending and receiving data to and from FPGA board. Regards, Relevant Skills and Experience 7+ years experience in Rnd Organization. Proposed Milestones ₹15000 INR - RS-232 Loop Code! ₹12777 INR - Complete work and simulaiton! Please share details of board on which you are going to test the code.

₹27,777 INR ndani ya siku 10