CMOS VLSI and should be done on virtuoso Cadence

Imefungwa Ilichapishwa Miaka 6 iliyopita Kulipwa wakati wa kujifungua
Imefungwa Kulipwa wakati wa kujifungua

c Integrated Circuit (ASIC) implementation of an N x

N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through

MOSIS.

CAD/CAM Ubunifu wa Circuit Uhandisi wa Umeme Very-large-scale integration (VLSI)

Kitambulisho cha Mradi: #15744696

Kuhusu mradi

5 mapendekezo Mradi wa mbali Ipo mtandaoni %project.latestActivity_relativeTime|badilisha%

5 wafanyakazi huru wanazabuni wastani wa $555 kwa kazi hii

rp502757

A proposal has not yet been provided

$777 USD kwa siku 3
(Maoni 0)
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rishabh143

I have been designing such kind of projects since 2015. I have experience on 32nm,45nm,65nm,90nm and 180nm. designed on tanner eda tool and cadence tool. Also hands on ADS software

$222 USD kwa siku 3
(Maoni 0)
0.0
ShilpaMehta1987

I can design your multiplier within a week if required on 28 nm technology as I don't have AMI access. Relevant Skills and Experience I have hands on practice on cadence virtuoso 28 nm technology

$222 USD kwa siku 5
(Maoni 0)
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